ARM Coretex-M0
Support 32-bit ARM Cortex-M0 (48MHz)
W7500P
The W7500P iMCU chip integrates an ARM Cortex-M0 core with TCP/IP, MAC, and PHY, delivering a powerful, all-in-one solution for IoT and networked devices. Featuring 128KB Flash, 16KB SRAM, and dual UART and SPI interfaces, it supports up to 25Mbps Ethernet speeds and operates in a 0 to +70°C range. Its compact 64 TQFP package (7x7 mm) and built-in networking functionalities make it ideal for smart home devices, IoT sensors, industrial control, and network communication devices, streamlining development with efficient processing and minimal power consumption.
34 GPIOs
Support 34GPIOs (15 IO x 2ea, 4 IO x 1ea)
SPI(2), UART(3), PWM(8)
Support SPI 2ch, UART 3ch, PWM 8ch
Timer(4), Watchdog(1)
Support 32/16-bit Timer(4), 32-bit Watchdog
StoreKey Features
DMA(6)
Support DMA 6ch
Flash 128KB/SRAM 16KB
Support Flash 128KB, SRAM 16KB, ROM for boot code 6KB
Ethernet MACPHY
Support 10BaseT/100BaseTX Ethernet MACPHY
3.3V 0℃ to 70℃
Support 3.3V Operation (2.7V to 3.6V)
64LQFP
Support 64LQFP type
Features
- ARM Cortex-M0( MAX 48MHz)
- Hardwired TCP/IP Core
- 8 Sockets
- SRAM for socket: 32 KB
- PHY : IC+(IP101G)
- Memories
- Flas: 128 KB, SRAM: 16KB, ROM for boot code: 6 KB
- Clock, reset and supply management
- POR (Power-On Reset)
- Internal Voltage Regulator : 3.3V to 1.5V
- 8-to-24MHz external crystal oscillator
- Internal 8MHz RC Oscillator
- PLL for CPU clock
- ADC : 12bit, 8ch, 1Msps
- DMA
- 6-channel DMA controller(Peripheral supported: UARTs, SPIs)
- GPIO
- 34 I/Os (15 IO x 2ea, 4 IO x 1ea)
- Debug mode
- Serial Wire Debug (SWD)
- Timer/PWM
- 1 Watchdog (32-bit down-counter)
- 4 Timers (32-bit or 16-bit down-counter)
- 8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)
- Communication Interfaces
- 3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)
- 2 SPI
- Crypto
- 1 RNG (Random Number Generator): 32-bit random number
- Package
- 64 LQFP (7x7 mm)
Documentation
Datasheet
| Name | Description | Notes | |
|---|---|---|---|
| W7500P Datasheet | Technical specifications and features of the W7500P chip | - |
W7500P Datasheet 
|
| W7500P Internal PHY Datasheet | How to control the internal PHY of W7500P using indirect register access via PHYR/PHYSR, with busy flag polling for read/write operations. | - |
W7500P Internal PHY Datasheet
|
Technical Documents
| Name | Description | Notes | |
|---|---|---|---|
| W7500P Reference Manual | Known issues, register details, and functional corrections for the W7500P chip | - |
W7500P Reference Manual
|
| W7500P Errata(EN) 7500P Errata(KR) | Known issues and corrections for the chips | - |
W7500P Errata(EN)
7500P Errata(KR)
|
| How to Access W7500x PHY Register | W7500x PHY is accessed indirectly via PHYR/PHYSR registers; read/write operations use busy flag polling to ensure proper completion | - |
How to Access W7500x PHY Register
|
| Limitation Note ARP problem in the NLB environment | Technical specifications and features of the W7500P chip | - |
Limitation Note ARP problem in the NLB environment
|
Getting Started
| Name | Description | Notes | |
|---|---|---|---|
| How to install KEIL | Step-by-step guide for installing KEIL development environment for W7500P | - |
How to install KEIL
|
| How to make KEIL new project for W7500 | Tutorial for creating new KEIL projects for W7500P development | - |
How to make KEIL new project for W7500
|
| How to use MDK for W7500 Peripherals Examples | Guide for using MDK with W7500P peripheral examples | - |
How to use MDK for W7500 Peripherals Examples
|
| How to use GCC for W7500 Peripherals Examples | Instructions for using GCC compiler with W7500P peripheral examples | - |
How to use GCC for W7500 Peripherals Examples
|
| How to use ISP tool | Guide for using In-System Programming tool with W7500P | - |
How to use ISP tool
|
W7500P
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