W55RP20

The W55RP20 chip, the first in the ioNIC series, offers unparalleled IoT connectivity with advanced security, low power consumption, and high-speed data processing. Ideal for both consumer and industrial applications.

Dual ARM Cortex-M0+

Support 32-bit Dual ARM Cortex-M0+ (133MHz)

23 GPIOs

Support 23GPIOs

SPI(2), UART(2), I2C(2), PWM(16), PIO(8)

Support SPI 2ch, UART 2ch, I2C 2ch, PWM 16ch, PIO

Timer(4), Watchdog(1)

Support 64-bit Timer(4), Watchdog

Key Features

DMA(12)

Support DMA 12ch

Flash 2M/SRAM 264KB

Support Flash 2Mbytes, SRAM 264KB in 6 independent banks

Ethernet MACPHY

Support 10BaseT / 100BaseTX Ethernet MACPHY

3.3V -40℃ to 85℃

Support 3.3V Operation (1.8V to 3.3V)

68GFN

Support 68QFN type

Features

  • Dual ARM Cortex-M0+ @ 133MHz
  • Hardwired TCP/IP stack
  • 2MByte Flash memory on-chip
  • 264kB on-chip SRAM in six independent banks
  • DMA controller
  • Fully-connected AHB crossbar
  • Interpolator and integer divider peripherals
  • On-chip programmable LDO to generate core voltage
  • 2 on-chip PLLs to generate USB and core clocks
  • 23 GPIO pins, 4 of which can be used as analogue inputs
  • Peripherals
    • 2 UARTs
    • 2 SPI controllers
    • 2 I2C controllers
    • 16 PWM channels
    • USB 1.1 controller and PHY, with host and device support
    • 8 PIO state machines
  • Supported Network Protocols
    • TCP
    • UDP
    • IPv4
    • ICMP
    • ARP
    • IGMP
    • PPPoE

Documentation

Datasheet

Name Description Notes
W55RP20 Datasheet (EN) Technical specifications and features of the W55RP20 chip -

Technical Documents

Name Description Notes
W5500 Datasheet (EN) Technical specifications and features of the W5500 chip -
RP2040 Datasheet (EN) Technical specifications and features of the W5500 chip -

W55RP20

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