W5500

The W5500 chip is a Hardwired Internet controller with an integrated full TCP/IP stack, enabling Internet connectivity via SPI with up to 80MHz speed. It combines 10/100 Ethernet MAC and PHY for stable connectivity and supports protocols like TCP, UDP, IPv4, among others. With 8 sockets and 32KB internal memory, it simplifies Ethernet application development and includes features like WOL and Power Down Mode for energy efficiency.

55Mbps

Support Up-to 55Mbps Network Performance

TCP/IPv4

Support Hardwired TCP/IPv4, IPv6

SPI

Support Fast-SPI (MODE 0/3)

Ethernet MACPHY

Support 10BaseT / 100BaseTX Ethernet MACPHY

Key Features

16KB Socket buffers

Support 16KB TX/RX Socket buffers

Hardwired Internet Protocols

TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE

3.3V -40℃ to 85℃

Support 3.3V Operation with 5V I/O tolerance

48LQFP

Support 48LQFP type

Features

  • Supports following Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
  • Supports 8 independent sockets simultaneously
  • Supports Power down mode
  • Supports Wake on LAN over UDP
  • Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
  • Internal 32Kbytes Memory for Tx/Rx Buffers
  • 10BaseT/100BaseTX Ethernet PHY embedded
  • Support Auto Negotiation (Full and half duplex, 10 and 100-based)
  • Not support IP Fragmentation
  • 3.3V operation with 5V I/O signal tolerance
  • LED outputs (Full/Half duplex, Link, Speed, Active)
  • 48 Pin LQFP Lead-Free Package (7x7mm, 0.5mm pitch)

Documentation

Datasheet

Name Description Notes
W5500 Datasheet (EN)
W5500 Datasheet (KR)
Technical specifications and features of the W5500 chip -

Technical Documents

Name Description Notes
spi-performance - -

W5500

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