W5100

The W5100 is an embedded Ethernet controller integrating a TCP/IP stack, Ethernet MAC, and PHY in one chip, supporting protocols like TCP, UDP, and IPv4. It offers 16-byte internal memory and enables easy development with 4 hardware sockets and options for BUS and SPI connections, simplifying Internet connectivity for embedded systems

25Mbps

Support Up-to 25Mbps Network Performance

TCP/IPv4

Support Hardwired TCP/IPv4

SPI, 8-bit BUS

Support SPI (MODE 0/3) and 8-bits Parallel BUS

Ethernet MACPHY

Support 10BaseT / 100BaseTX Ethernet MACPHY

Key Features

16KB Socket buffers

Support 16KB TX/RX Socket buffers

Hardwired Internet Protocols

TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE

3.3V -40℃ to 85℃

Support 3.3V Operation with 5V I/O tolerance

48LQFP

Support 48LQFP type

Features

  • Support Hardwired Internet Protocols: TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE
  • Support 4 Independent Hardware SOCKETs simultaneously
  • Support SOCKET-less Command: ARP-Request, PING-Request
  • Support Ethernet Power Down Mode & Main Clock gating for power save
  • Support Wake on LAN over UDP
  • Support Serial & Parallel Host Interface: High Speed SPI(MODE 0/3), Parallel System Bus with 2 Address signal & 8bits Data
  • Internal 16 Kbytes Memory for TX/ RX Buffers
  • Not support IP Fragmentation
  • Not Maintain ARP-cache Table
  • 10BaseT/100BaseTX Ethernet PHY Integrated
  • Support Auto Negotiation (Full/Half Duplex, 10/100 Speed)
  • Support Auto-MDIX when Auto-Negotiation Mode.
  • 3.3V operation with 5V I/O signal tolerance
  • LED outputs (Full/Half Duplex, Link, 10/100 Speed, Active)
  • Two types of packages: 48 Pin LQFP & QFN Lead-Free Package (7x7mm, 0.5mm pitch)

Documentation

Datasheet

Name Description Notes
W5100 Datasheet (EN) Technical specifications and features of the W5100 chip -

Technical Documents

Name Description Notes
W5100 Errarta Known issues and corrections for the W5100 chip -

W5100

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